The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench which is generally wider than the contact hole in an upper portion. The via serves as a contact to a device while the trench contains the conductive line for connecting the device to, for example, other devices.
As critical dimensions (CD) continue to shrink, ultra-low k dielectric (ULK) material has been proposed. However, the porosity nature of the ultra-low k dielectric material often results in integration problems, such as severe undercut and over etched in the etch profile. One example of such problems being that the depth delta between dense and wide features increases significantly from dual damascene trench reactive ion etching (RIE) plus dilute hydrofluoric acid (DHF) clean to the metallization process.
From the foregoing discussion, it is desirable to improve the depth delta between the dense and wide features in dual damascene structures in order to obtain good integration of interconnect.